Journals
"Automatic linux malware detection using binary inspection and runtime opcode tracing". Microprocessors and Microsystems 120, 105237, 1-8 (2026). DOI: https://doi.org/10.1016/j.micpro.2025.105237
"Federated transfer learning-based intrusion detection system in 5G networks". Expert Systems with Applications 305, 130868, 1-13 (2026). DOI: https://doi.org/10.1016/j.eswa.2025.130868
"Multi Hardware-Attack Dataset and ML-Based Detection using Processor Stress Patterns on x86". WiPiEC Journal 11(1), 7, 36-42 (2025). DOI: https://doi.org/10.64552/wipiec.v11i1.94
"Enhancing cibersecurity in railways: Machine Learning Approaches for Attack Detection". International Journal of Critical Infrastructure Protection, 50, 100788, 1-15 (2025). DOI: https://doi.org/10.1016/j.ijcip.2025.100788
"A Differential Privacy Protection-Based Federated Deep Learning Framework to Fog-Embedded Architectures". Engineering Applications of Artificial Intelligence 130, 107689 (2024). DOI:https://doi.org/10.1016/j.engappai.2023.107689
"A Survey on Hardware-Based Malware Detection Approaches", IEEE Access 12, 54115-54128 (2024). DOI: https://doi.org/10.1109/ACCESS.2024.3388716
"A Survey of Machine and Deep Learning Methods for Privacy Protection in the Internet of Things". Sensors 23, 1252 (2023). DOI: https://doi.org/10.3390/s23031252
"Deep‑Learning Based Detection for Cyber‑Attacks in IoT Networks: A Distributed Attack Detection Framework". J Netw Syst Manage 31, 33 (2023). DOI: https://doi.org/10.1007/s10922-023-09722-7
“Silent Data Corruptions: Microarchitectural Perspectives“, IEEE Transactions on Computers. 72 (11), 2023. DOI: https://doi.org/10.1109/TC.2023.3285094
Datasets
RISC-V hardware attack traces on gem5 O3 CPU performance and instruction counters (HARPY-V-GEM5 Dataset), Oct 2025, DOI: https://doi.org/10.34810/data2711.
RISC-V hardware attack traces on on-chip hardware performance counters (HARPY-V Dataset), Sept 2025, DOI: https://doi.org/10.34810/data2538.
Replication Data for: Hardware Attack detectoR via Performance counters anskYsis Dataset (HARPY Dataset), Jan 2025, DOI: https://doi.org/10.34810/data1982.
Preprints
"Enabling an OpenStack-based cloud on top of RISC-V hardware", ArXiV, 2024, DOI: https://doi.org/10.48550/arXiv.2407.12008.
"A survey of hardware-based malware detection approach", ArXiV, 2023, DOI: https://doi.org/10.48550/arXiv.2303.12525.
Conferences
"Enabling Realistic Virtualized Cloud Workload Evaluation in RISC-V". Computer Architecture Modeling and Simulation (CAMS 2025) (paper)
"VITAMIN-VOpen Challenges for a Production-ready Cloud Environment on top of RISC-V hardware". RISC-V Summit Europe 2025 (poster)
"Enabling Syscall Interception on RISC-V". RISC-V Summit Europe 2025 (poster)
"NAVIgator: Exploring the Voltage Limits of AMD NAVI GPUs for Energy Efficient Computing". IEEE Symposium on On-Line Testing (IOLTS 2025) (paper)
"Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration". IEEE Symposium on On-Line Testing (IOLTS 2025) (paper)
"Accurate Analysis of Silent Data Corruptions in Programmable AI Accelerator Microarchitectures". IEEE Symposium on On-Line Testing (IOLTS 2025) (paper)
"vACE: Exploring the Design Space of Vector Processing Units for Soft Error Vulnerability". 2025 IEEE International Symposium on Workload Characterization (paper)
"Benchmarking Support for RISC-V CPUs in Serverless Computing". 2025 IEEE International Symposium on Workload Characterization (poster)
"From Gates to SDCs: Understanding Fault Propagation Through the Compute Stack". DATE 2025 (paper)
"Runtime Energy Monitoring for RISC-V Soft-Cores". The 19-th International Conference on Complex, Intelligent, and Software Intensive Systems (CISIS-2025) (paper)
"Zero-Day Hardware-Supported Malware Detection of Stack Buffer Overflow attacks: an application exploiting the CV32e40p RISC-V core". 2025 IEEE 26th Latin American Test Symposium (LATS) (paper)
"Multi Hardware-Attack Dataset and ML-Based Detection using Processor Stress Patterns on x86". 28th Euromicro Conference on Digital System Design (DSD 2025) (paper)
"Enabling the syscall intercept library for RISC-V". Supercomputing '25 Conference (paper)
"Veritas – Demystifying Silent Data Corruptions: μArch-Level Modeling and Fleet Data of Modern x86 CPUs". HPCA 2025 (paper)
"Vitamin-V: Serverless Cloud Computing Porting on RISC-V". International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) 2024 (paper)
"Vitamin-V: Serverless Cloud Software Porting Progress". International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) 2024 (paper)
"Security and RAS in the Computing Continuum". 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2024) (paper)
"Malware Detection on Linux Using Runtime Opcode Tracing". 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2024) (paper)
"Hardware-based stack buffer overflow attack detection on RISC-V architectures". RISC-V Summit Europe 2024 (paper)
"Enabling an OpenStack-based cloud on top of RISC-V hardware". RISC-V Summit Europe 2024 (poster)
"Vitamin-V: Expanding Open-Source RISC-V Cloud Environments". RISC-V Summit Europe 2024 (paper)
"Fast, Accurate and Distributed Simulation of novel HPC systems incorporating ARM and RISC-V CPUs". HPDC 2024 (paper)
"Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation". ISCA 2024 (paper)
"SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs". ISPASS 2024 (paper)
"Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale". IEEE European Test Symposium (paper)
"Detection of Hardware Based Attacks Using Performance Counters", HiPEAC 2024 (poster)
"Malware detection using opcodes and machine learning", HiPEAC 2024 (poster)
"VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V-Based Cloud Services — Hardware-based Stack Buffer Overflow Attack Detection on RISC-V Architectures". IEEE European Test Symposium 2024. (poster)
"Silent Data Corruptions: The Stealthy Saboteurs of Digital Integrity", 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS) (paper)
"VITAMIN-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services". 26th Euromicro Conference Series on Digital System Design (DSD 2023) (paper)
"Hypervisor Extension for a RISC-V Processor". RISC-V Summit Europe 2023 (poster) (paper)
"VOSySmonitoRV: a mixed-criticality solution on Linux-capable RISC-V platforms". RISC-V Summit Europe 2023 (poster)
"Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the VITAMIN-V Horizon Europe Project perspective ". 2023 IEEE European Test Symposium, (paper)
"Silent data errors: Sources, Detection and modeling". VTS, IEEE 41st VLSI Test Symposium (paper)
"Challenges and Opportunities for RISC-V Architectures towards Genomics-based Workloads".. ISC, First International workshop on RISC-V for HPC (paper)
"VITAMIN-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services". HiPEAC 2023 (poster)
Invited talks
"Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Service", AI Computing Continuum, Brussels 2025, (presentation)
"The RISC-V Hypervisor Extension in gem5". ISCA 2025 (presentation)
"Building, running and testing Kubernetes on RISC-V". HiPEAC 2025 (presentation)
"Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Service", Computing Continuum of Cloud, Edge and IoT Technologies Workshop, HiPEAC 2025, (presentation)
"Building, running and testing Kubernetes on RISC-V". 1st Open-Source RISC-V Software Workshop. Co-located with the RISC-V Summit Europe 2024 (presentation)
"Vitamin-V: Expanding Open-Source RISC-V Cloud Environments", RISC-V Summit Europe 2024. (presentation)
"Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Service", Nexus Forum Submit 2024 (presentation)
"Vitamin-V: Open-Source RISC-V Cloud Environments", EUCEI RIAs Showcase #6 - Presenting the future of open source for cloud services. (presentation)
"Presentación del proyecto europeo Vitamin-V",XIV Seminario de Invierno CAPAP-H, Red-RISC-V. (presentation)
"Vitamin-V: Pushing for a Trustworthy RISC-V-based Cloud Stack", Computing Continuum of Cloud, Edge and IoT Technologies Workshop, HiPEAC 2024, (presentation)
“Dynamic Memory Expansion with Hardware-Accelerated Compression”, 33rd International Conference on Field-Programmable Logic and Applications (presentation)
"VITAMIN-V: pushing for a complete hardware/software RISC-V stack for IoT/Cloud". HiPEAC 2023 (presentation)
"VITAMIN-V project overview". HiPEAC 2023
Showcases/Demos
"OpenStack port to RISC-V", Mobile World Congress 2024. (video)
Outreach activities
"Integrating artificial intelligence into cybersecurity for critical infrastructure protection ". Research café 18: Data security (presentation pp.18-35)
"Vitamin-V: una plataforma pionera de codi obert per a la nova generació \\d’aplicacions al núvol". GenCat
"QEMU-based emulation platform integrated with a first limited version of the compressed memory manager software (demo)". Industrial Exhibition of the SuperComputing 2023 (demo)
"Semidynamics attendence on the SEDEX 2023, a Semiconductor Exhibition in Korea". SEDEX Korea Semiconductor (exhibition)
“Plans about RISC-V extensions for memory compression”, presentation at the Göteborg RISC-V Group (Gbg RISC-V meetup #1)
“Com els supercomputadors poden ajudar a entendre l'Alzheimer i altres malalties?”, presentation at Nit de la Recerca at Berga
"VITAMIN-V: Vitamines per un núvol de codi obert basat en RISC-V". Fira del coneixement 2023 (poster)